Oh, I forgot about the registers! Registers are memory in the CPU. They range from x0 to x31. A register has 32 bits in RV32I. The content of x0 is always zero, but we'll get to that later. The registers also have other names (on the right). But let's ignore that for now. 2

In RISC-V, there are many extensions and designations, including 64-bit and 128-bit. But we will ignore that and not go into it. However, there is a little sweet brother RV32E, which has only 16 registers instead of 32. Look here, but ignore it for now. https://five-embeddev.com/risc... 3

It would be very helpful to understand the instructions and be able to write assembler programs, wouldn't it? 4

Let's simply compute x3 = x4 + x5. Regardless of what is already stored in x4 or x5. It's simple, we happen to have registers named x4 and x5. And RISC-V is a 3-address computer, with one target and two operands. How cool! 5

The instruction would simply be 'add x3, x4, x5'. And the instruction is of the R-type, because only registers are involved. So, that's it for today. Try playing around with the instructions! 6

I have implemented the three most important basic designs: multicycle, single cycle, and a 5-stage pipeline. In this thread, I am trying to explain the single cycle CPU, which also exists in the GitHub directory for download. 7

I allowed myself the fun of running my single cycle CPU at 80MHz, which corresponds to 80 million instructions per second. That was a very nice experience. The bottleneck is the UART, which transmitted data at 3MBaud. https://x.com/splinedrive/stat... 8

The single cycle CPU can be found here. I will explain the concepts of the different types later https://github.com/splinedrive... 9

Hello everyone, I am currently missing a word to see how simple the structure of a RISC-V processor is. Could you try out my C emulator for an RV32I? You will get to enjoy MicroPython. Yes, you heard that right! clone it, make it, run it, micropython it! https://github.com/splinedrive...

Let's get back to the CPU commands. A classic CPU has the following types of commands that can be categorized: logical commands, arithmetic commands, transport commands, and control commands. 11

Von Neumann defined the principle of the CPU in 1945 with the following points: Memory: Data and instructions are stored here. CPU: It consists of a control unit and arithmetic unit that execute the categorized commands described in 11 12

Input/Output (I/O): Communication with other hardware components. Buses: They facilitate communication between different hardware components. 13

There is also the Harvard architecture, which was developed in the 1940s as well. The main difference is that instructions and data are stored in separate memories. This separation increases performance by allowing simultaneous access to both types of memory. 14

In the thread, I mentioned the three classic approaches to computer architecture: single-cycle, multi-cycle, and pipelined CPU architecture. Single-cycle and pipelined architectures utilize the Harvard architecture, while multi-cycle architecture employs the von Neumann arch. 15

That was a bit too abstract. Here are two images taken from Wikipedia for Harvard and Neumann architecture. Read this through, it's very interesting. https://en.wikipedia.org/wiki/... https://en.wikipedia.org/wiki/... 16

Let's come back to the instructions we saw at the beginning. Play around with them! I can recommend this online simulator for you! That helped me a lot. I think logic design of a CPU without understanding instructions doesn't make sense. https://www.cs.cornell.edu/cou... 17

This is really fun and you learn a lot. Take a look at the CPU registers! Learn assembly language, that's the only way you can understand the CPU. 18

I hope you have familiarized yourselves with the instructions in the simulator. All algorithms and computer programs are mapped onto these few commands. I find it incredible to get Micropython running on the small emulator, where a RISC-V machine is being simulated. 19

Let's start the demo and enjoy RISC-V being emulated with Micropython. You can download my emulator here, I think it's really crazy. https://github.com/splinedrive...

The emulator is actually written in C, but it somewhat represents how I approach things in Verilog. This applies to all the processor types I have implemented in a similar way. 21

You should study this program a little, then we'll go through the commands individually again. The command structures, types or categories. Then we can move on to concrete register transfer and discuss the components. 22

I would have taken the same approach, but I went through the hard school of trying things out on the FPGA without simulation, since I had no idea what was possible two years ago. You must get a feeling for what is being generated in the synthesis. 23

I repeat, we are taking an RV32I. It is a 32-bit RISC-V processor, but there are also 64-bit and 128-bit versions available. A simple processor fetches 32-bit instructions, as you can see in this image. These instructions represent various command types. 24

Let's start with R-type. The instruction only fetches operands from registers and writes the result back to a register. As I mentioned, RISC is mostly a 3-address machine. The format is Target register, Operand1 Operator Operand2. See the table below. 25

Now let's move on to the immediate instruction. It's similar to the R-type instruction, but the second operand is not fetched from a register. Instead, it is obtained from the instruction itself and is 12 bits long, representing an 26

unsigned value from 0 to 4095. For example, 'addi x1, x2, 5', where 5 is embedded in the instruction.The format is Target Register, Operand1 Operator Operand. In the case of a non-load instruction, 26

the load instructions are also immediate instructions, but they read from external memory instead of registers. The immediate value is added as an offset value to a register that serves as a pointer in memory to read. c-syntax: target R = *(RS1 + imm) 27

The S-type instruction. It is used for write operations on external memory, so no registers are involved as target. The same concept applies here: we have a register as the base and an immediate value as the offset, which are added together. c-syntax: *(RS1 + imm) = RS2 28

With load/store operations, there are different variations based on the data types being operated on, but we will discuss those later during the implementation. 29

The next instructions are the B-type ones. They are used for conditional branching, which helps to implement if, else if statements. The same concept applies here: when the condition is true, jump to the program counter plus the immediate value. 30